This invention relates to a method of forming electrodes on the surface of a semiconductor substrate, and more particularly to a method of mounting electrodes on the surface of a semiconductor substrate, while extremely reducing the width of the electrodes and the interelectrode distance with high precision, as well as to a semiconductor device manufactured by said method.
The known process of effecting the above-mentioned manufacture is set forth in the U.S. Pat. No. 3,822,467 filed Apr. 25, 1973. A method proposed in the United States Patent to manufacture a semiconductor device having a conductor pattern comprises the following steps:
(A) forming a semiconductor body whose surface is covered with a perforated insulation layer and which includes a semiconductor zone accessible through the aperture;
(B) mounting on the surface of the insulation layer an auxiliary layer which is formed of a metal essentially different from that of the conductor pattern and is provided with at least one recess having a predetermined outline corresponding to that of the pattern of conductors which are subsequently deposited;
(C) depositing on the semiconductor body a layer of electrically conductive material, whose first portion is spread over the auxiliary layer and whose second portion is disposed in the recess, extends over the insulation layer and is connected to the semiconductor zone; and
(D) removing the auxiliary layer and the first portion of the conductive layer while retaining on the semiconductor body the second portion of the conductive layer which bears the conductor pattern.
The above mentioned step (C) is undertaken by vapor deposition or sputtering. The concrete process runs as follows. The step (C) is to provide a conductive layer by gas phase growth and at reduced pressure, utilize a local source of material, transport the material of the conductive layer mainly in a direction perpendicular to the surface of the semiconductor body.
Where the material of the conductive layer is deposited in a direction inclined to the surface of the semiconductor body, instead of in a direction perpendicular there to, then the material of the conductive layer is also deposited on the lateral wall of the auxiliary layer, undesirably giving rise to a contact between the auxiliary layer and the second portion of the conductive layer, and presenting difficulties in the satisfactory performance of the step (D).
Where the material of the conductive layer is deposited perpendicularly on the surface of the semiconductor body as described in the aforesaid U.S. Patent, then a conductive layer formed on the upper portion or stepped portion of the aperture drilled in the insulation layer will have a far smaller thickness than the other portions of said conductive layer, namely those mounted on the insulation layer and that portion of the semiconductor body which is exposed through the aperture. Therefore the conductive layer is likely to be broken at such then portion.
In the step (D), it is necessary to fully remove the auxiliary metal layer from the surface of the insulation layer. If any amount of the auxiliary metal layer is retained on the surface of the insulation layer, a contact arises between the residual auxiliary metal layer and conductor pattern, possibly resulting in interelectrode short-circuiting. Moreover, the insulation layer underlying the residual auxiliary metal layer acts as a dielectric element, leading to the occurrence of stray capacitance. This stray capacitance is most objectionable to a circuit portionlarly required to have high frequency characteristics.